1. Technical Field
The present invention relates to a semiconductor device (embedded DRAM) having a DRAM region and a logic region embedded therein.
2. Related Art
In a semiconductor device (embedded DRAM) having a DRAM region and a logic region embedded therein, transistors are formed in each of the DRAM region and the logic region so as to be adapted to the individual characteristics. In the conventional DRAM region, it has been necessary to make the gate insulating film thicker, in order to achieve a high breakdown voltage.
The cells are, however, desired to be shrunk, for the purpose of increasing the memory capacity and reducing the cost. For this purpose, the gate length L and the gate width W of the cell transistors in the DRAM region are desired to be shrunk. On the other hand, it may be necessary to thin the gate insulating film (reduction in the equivalent oxide thickness (EOT)) in order to downsize the gates of the cell transistors in the DRAM region.
U.S. Pat. No. 6,108,229 describes that the switching transistors of memory cells and logic transistors in the peripheral logic circuit have the same gate insulating film. In the invention described in this literature, the switching transistors of the memory cells and the logic transistors in the peripheral logic circuit are made equal also in the threshold voltage. Prior art described in this literature relates to an exemplary process of adding a step of masking, for the purpose of equalizing the thickness of the gate insulating films of the switching transistors of the memory cells and the logic transistors in the peripheral circuit, while making difference only in the threshold voltage (Table 1).
Further, U.S. Pat. No. 6,815,281 describes a configuration in which silicide is formed in the logic portion and the memory cell portion.
However, shrinkage in the gate size of the cell transistors in the DRAM region, and consequent adjustment of the thickness of the gate insulating film nearly equal to the thickness of the gate insulating film of the logic transistors, have raised problems of increase in Ioff (degradation in retention characteristics) and lowering in the breakdown voltage. For example, it is described also in U.S. Pat. No. 6,108,229 that adoption of the same configuration both by the switching transistors in the memory cells and the logic transistors in the peripheral logic circuit increases leakage current from the switching transistors in the memory cells, so that it is necessary to provide a self-refresh mechanism, an error code checking (ECC) and a correction means (column 24, lines 31 to 52).